M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 153

• Manufacturer Part Number: M30262F8GP#U7
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F8GP#U7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UART2 Special Mode Register 2
UART2 Special Mode Register 2
Table 1.15.14. Functions changed by I
Table 1.15.15. Timing characteristics of detecting the start condition and the stop condition (Note 1)
3
4
5
2
1
UARTi special mode register 2 (address 0376
Bit 0 of the UART2 special mode register 2 (address 0376
1.15.14 shows the types of control to be changed by I
is set to “1”. Table 1.15.15 shows the timing characteristics of detecting the start condition and the stop
condition.
Factor of interrupt number 16
DMA1 factor at the time when 1101 is
Factor of interrupt number 15
assigned to the DMA request factor
selection bits.
Timing for transferring data from the
UART2 reception shift register to the
reception buffer.
Timing for generating a UART2
reception/ACK interrupt request
Note: Cycles is in terms of the input oscillation frequency f(X
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
Preliminary Specifications Rev. 0.9
(Start condition)
(Stop condition)
Specifications in this manual are tentative and subject to change.
Function
SDA
SDA
SCL
Renesas Technology Corp.
No acknowledgment detection (NACK)
Acknowledgment detection (ACK)
Acknowledgment detection (ACK)
The rising edge of the final bit of the
The rising edge of the final bit of the
reception clock
reception clock
2
C mode select bit 2
Duration for
setting up
16
) is used to further control UART2 in I
IICM2 = 0
2
C mode select bit 2 when the I
16
Duration for
) is used as the I
holding
IN
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
) of the main clock.
The falling edge of the final bit of the
UART2 transmission (the rising edge
of the final bit of the clock)
UART2 reception (the falling edge of
the final bit of the clock)
The falling edge of the final bit of the
reception clock
UART2 reception (the falling edge of
the final bit of the clock)
reception clock
2
C mode select bit 2. Table
IICM2 = 1
2
M16C/26 Group
2
C mode select bit
C mode.
145