M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 65

• Manufacturer Part Number: M30262F8GP#U7
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F8GP#U7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupts
Returning from an Interrupt Routine
Interrupt Priority
Figure 1.9.8. Hardware interrupts priorities
Executing a REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG)
as it was immediately before the start of interrupt sequence and the contents of the program counter (PC),
both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
To return the other registers saved by software within the interrupt routine, use the POPM or similar instruc-
tion before executing the REIT instruction.
If there are two or more interrupt requests generated at the same time, the interrupt assigned with a higher
priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned with a higher
hardware priority is accepted.
Priorities for the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are controlled by hardware.
Figure 1.9.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, the circuit in Figure 1.9.9 selects the interrupt
based on the priority level shown.
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
Renesas Technology Corp.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C/26 Group
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