M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 18

• Manufacturer Part Number: M30262F8GP#U7
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F8GP#U7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CPU
10
(3) Frame base register (FB)
(4) Program counter (PC)
(5) Interrupt table register (INTB)
(6) Stack pointer (USP/ISP)
(7) Static base register (SB)
(8) Flag register (FLG)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
• Bit 0: Carry flag (C flag)
• Bit 1: Debug flag (D flag)
• Bit 2: Zero flag (Z flag)
• Bit 3: Sign flag (S flag)
• Bit 4: Register bank select flag (B flag)
• Bit 5: Overflow flag (O flag)
• Bit 6: Interrupt enable flag (I flag)
• Bit 7: Stack pointer select flag (U flag)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.3 shows the flag
register (FLG). The following explains the function of each flag:
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
This flag is set to “1” when an arithmetic operation resulted in overflow.
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared
to “0” when the interrupt is acknowledged.
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
Renesas Technology Corp.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C/26 Group