M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 17

IC M16C/TINY MCU FLASH 48LQFP

M30262F8GP#U7

Manufacturer Part Number
M30262F8GP#U7
Description
IC M16C/TINY MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheets

Specifications of M30262F8GP#U7

Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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CPU
Central Processing Unit (CPU)
Figure 1.4.2. Central processing unit register
The CPU has a total of 13 registers shown in Figure 1.4.2. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
(2) Address registers (A0 and A1)
R0
R1
R2
R3
A0
FB
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 can each be used as dual 8-bit data registers. As such, their high-order bytes are
designated R0H/R1H, while their low-order bytes become R0L/R1L, respectively. In some instructions,
registers R2 and R0, as well as R3 and R1, can be combined to serve as 32-bit data registers (R2R0/R3R1).
Address registers (A0 and A1) consist of 16 bits each. Individually, they can be used for three types of
register-based addressing: register direct, address register indirect, and address register relative. They
are also used for transfer and arithmetic/logic operations, as well as three special instruction addressing
modes: address register relative with 20-bit displacement, 32-bit address register indirect, and 32-bit
register direct. These last two modes combine A0 and A1 for use as a single 32-bit register (A1A0).
A1
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Note: These registers consist of two register banks.
b15
b15
b15
b15
b15
b15
b15
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
H
H
b8 7
b8 7
L
L
b0
b0
b0
b0
b0
b0
b0
Renesas Technology Corp.
Data
registers
Address
registers
Frame base
registers
PC
INTB
b19
b19
USP
SB
ISP
FLG
H
b15
b15
b15
b15
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
L
b0
b0
b0
b0
b0
b0
M16C/26 Group
Interrupt table
register
Static base
register
Program counter
User stack pointer
Interrupt stack
pointer
Flag register
9

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