M30262F8GP#U7 Renesas Electronics America, M30262F8GP#U7 Datasheet - Page 39

• Manufacturer Part Number: M30262F8GP#U7
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F8GP#U7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
(2) Sub-clock
(3) BCLK
(4) Peripheral function clock(f
(5) f
(6) f
Figure 1.8.4a shows the system clock control registers 0 and 1 and Figure 1.8.4b shows peripheral clock
select register.
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the X
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power
dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed
mode, the value before high-speed/medium-speed mode is retained.
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port X
selected as the BCLK by using the system clock select bit (bit 7 at address 0006
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the X
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when the port X
at a reset.
When the X
The BCLK is the clock that drives the CPU, and is f
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
The main clock division select bit 0(bit 6 at address 0006
speed/medium-speed to stop mode, shifting to low power dissipation mode and at reset. When shifting
from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed
mode is retained.
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 0006
By setting the timer A, B clock select bit (bit 0 at address 001E
001E
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
C32
C
16
) to "1" respectively, f
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
CIN
/X
COUT
is used, set ports P8
16
1
) to “1” and then executing a WAIT instruction.
C
and f
select bit (bit 4 at address 0006
1SIO2
Renesas Technology Corp.
1
, f
8
can be changed to the main clock divided by 2.
, f
C
6
32
CIN
IN
and P8
select bit (bit 4 at address 0006
, f
-X
-X
1SIO2
OUT
COUT
C
7
or the clock is derived by dividing the main clock by
drive capacity select bit (bit 5 at address 0007
as the input ports without pull-up.
, f
drive capacity select bit (bit 3 at address 0006
8SIO2
16
16
) changes to “1” when shifting from high-
16
) and SIO clock select bit (bit 1 at address
,f
) is set to “0” , shifting to stop mode and
32SIO2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
,f
AD
)
16
), the sub-clock can be
16
). However, be sure
M16C/26 Group
16
). Stopping the
16
16
).
).
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