R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 106
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 106 of 1342
- Download datasheet (7Mb)
Section 3 Instruction Set
Rev.1.00 Dec. 13, 2005 Page 54 of 1286
REJ09B0158-0100
Addressing
Mode
Register
indirect with
displacement
Indexed
register
indirect
GBR indirect
with displace-
ment
Indexed GBR
indirect
Instruction
Format
@(disp:4, Rn)
@(R0, Rn)
@(disp:8, GBR) Effective address is register GBR contents with
@(R0, GBR)
Effective Address Calculation Method
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the operand
size.
Effective address is sum of register Rn and R0
contents.
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the operand
size.
Effective address is sum of register GBR and R0
contents.
(zero-extended)
(zero-extended)
GBR
1/2/4
GBR
1/2/4
disp
disp
Rn
R0
R0
Rn
×
×
+
+
+
+
Rn + disp × 1/2/4
+ disp × 1/2/4
GBR + R0
Rn + R0
GBR
Calculation
Formula
Byte: Rn + disp
→ EA
Word: Rn +
disp × 2 → EA
Longword:
Rn + disp × 4
→ EA
Rn + R0 → EA
Byte: GBR +
disp → EA
Word: GBR +
disp × 2 → EA
Longword:
GBR + disp × 4
→ EA
GBR + R0 →
EA
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