R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 688

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Watchdog Timer and Reset
And the time until WDTCNT overflows becomes the minimum value when H'001 is set to
WDTST. The minimum overflow time is approximately 5.243 ms (= 2^1 [bit]
16.4.5
Writing H'55 to WDTBST with longword access clears WDTBCNT and writing the overflow
setting value to WDTST clears WDTCNT.
16.5
16.5.1
A power-on reset is to initialize the on-chip PLL circuit when this LSI goes to the power-on reset
state by the PERSET pin low level input and then it is necessary to ensure the synchronization
settling time of the PLL circuit. Therefore, do not input high level to the PRESET pin during the
synchronization settling time of the PLL. The PLL synchronization settling time is the total value
of the PLL1 synchronization settling time and the PLL2 synchronization settling time.
After the PRESET pin input level is changed from low level to high level, the reset state is
continued during the reset holding time in the LSI. The reset holding time is 20 clock cycles of the
XTAL clock and thereafter equal to or more than 45 clock cycles of the peripheral clock (Pck).
The STATUS [1:0] pins output timing that indicates the reset state is asynchronous, and that
indicates a normal operation is synchronous with the peripheral clock (Pck) and asynchronous
with both the XTAL clock and the CLKOUT pin output clock.
Turning On Power Supply
When turning on the power supply, the PRESET pin input level should be low level. And the
TRST pin input level should be low level to initialize the H-UDI.
Rev.1.00 Dec. 13, 2005 Page 636 of 1286
REJ09B0158-0100
Clearing WDT Counter
Status Pin Change Timing during Reset
Power-On Reset by PRESET
×
5.243 [ms]).