R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 450

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 Local Bus State Controller (LBSC)
If a DMA transfer is executed for the space that the source address is in the LBSC space and the
destination address is out of the LBSC space and the LCKN bit in CHCR is cleared to 0, the bus is
not released after the DMA write access is ended even if the bus release signal (BREQ) is asserted.
And then execute read or write access to any address of the LBSC space from the CPU, the bus is
released after the access. This procedure does not need when the LCKN bit is set to 0.
If a DMA transfer is executed for the space that the source address is out of the LBSC space and
the destination address is in the LBSC space and the LCKN bit in CHCR is cleared to 0, the bus is
released in the cycle between read access and write access.
Rev.1.00 Dec. 13, 2005 Page 398 of 1286
REJ09B0158-0100
Figure 11.36 Example of the Bus Release Restraint by the DMAC CHCR LCKN bit
DMAC CHCR LCKN = 0, Source address: LBSC space, Destination address: LBSC space
DMAC CHCR LCKN = 0, Source address: LBSC space, Destination address: not LBSC space
DMAC CHCR LCKN = 0, Source address: not LBSC space, Destination address: LBSC space
CSn
BREQ
BACK
CSn
BREQ
BACK
CSn
BREQ
BACK
DMA read access
to other than the LBSC space
DMA read access
to the LBSC space
DMA read access
to the LBSC space
DMA write access
to other than the LBSC space
DMA write access
to the LBSC space
DMA write access
to the LBSC space
CPU access
to the LBSC space