R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 812

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Dec. 13, 2005 Page 760 of 1286
REJ09B0158-0100
Bit
7
6
5
4
3
Bit Name
RTRG1
RTRG0
TTRG1
TTRG0
MCE
*
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Receive FIFO Data Number Trigger
These bits are used to set the number of receive data
bytes that sets the RDF flag in SCFSR.
The RDF flag is set when the number of receive data
bytes in SCFRDR is equal to or greater than the trigger
set number shown below.
00:1
01:16
10:32
11:48
Transmit FIFO Data Number Trigger
These bits are used to set the number of remaining
transmit data bytes that sets the TDFE flag in SCFSR.
The TDFE flag is set when the number of transmit data
bytes in SCFTDR is equal to or less than the trigger set
number shown below.
00: 32 (32)
01:16 (48)
10: 2 (62)
11: 0 (64)
Note: Figures in parentheses are the number of empty
Modem Control Enable
Enables the SCIF0_CTS and SCIF0_RTS modem
control signals. Always set the MCE bit to 0 in clocked
synchronous mode.
0: Modem signals disabled
1: Modem signals enabled
Note: When the MCE bit is 0, SCIF0_CTS is fixed at
bytes in SCFTDR when the flag is set.
active-0 regardless of the input value, and
SCIF0_RTS output is also fixed at 0.