R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 551

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
3
2
1
Bit Name
TAI
MAI
RDPEI
Initial
Value
0
0
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Target-Abort Interrupt
Indicates that a transaction is terminated with a
target-abort when a device other than the PCIC
functions as a bus master.
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
Master-Abort Interrupt
Indicates that a transaction is terminated with a
master-abort when a device other than the PCIC
functions as a bus master.
0: Master-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master-abort interrupt occurs
[Set condition]
When a master-abort interrupt occurs.
Read Parity Error Interrupt
The PERR assertion is detected during a data read
when a device other than the PCIC functions as a
bus master.
0: Read parity error interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Read parity error interrupt occurs
[Set condition]
When a read parity error interrupt is detected by the
PERR assertion.
Rev.1.00 Dec. 13, 2005 Page 499 of 1286
Section 13 PCI Controller (PCIC)
REJ09B0158-0100