R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 252
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 Caches
• Data array
• LRU
8.2
The following registers are related to cache.
Table 8.3
Note:
Table 8.4
Rev.1.00 Dec. 13, 2005 Page 200 of 1286
REJ09B0158-0100
Register Name
Cache control register
Queue address control register 0
Queue address control register 1
On-chip memory control register
Register Name
Cache control register
Queue address control register 0
Queue address control register 1
On-chip memory control register
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
In a 4-way set-associative method, up to 4 items of data can be registered in the cache at each
entry address. When an entry is registered, the LRU bit indicates which of the 4 ways it is to be
registered in. The LRU mechanism uses 6 bits of each entry, and its usage is controlled by
hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the
less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a
manual reset. The LRU bits cannot be read from or written to by software.
*
Register Descriptions
These P4 addresses are for the P4 area in the virtual address space. These area 7
addresses are accessed from area 7 in the physical address space by means of the
TLB.
Register Configuration
Register States in Each Processing State
Abbreviation
CCR
QACR0
QACR1
RAMCR
Abbreviation
CCR
QACR0
QACR1
RAMCR
R/W
R/W
R/W
R/W
R/W
Power-on Reset
H
Undefined
Undefined
H
'
'
0000 0000
0000 0000
P4 Address*
H
H
H
H
'
'
'
'
FF00 001C
FF00 0038
FF00 003C
FF00 0074
Manual Reset
H
Undefined
Undefined
H
'
'
0000 0000
0000 0000
Area 7 Address*
H
H
H
H
'
'
'
'
1F00 001C
1F00 0038
1F00 003C
1F00 0074
Sleep
Retained
Retained
Retained
Retained
Access
Size
32
32
32
32
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