R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 856

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 22 Serial I/O with FIFO (SIOF)
Table 22.4 shows the operation in each transfer mode.
Table 22.4 Operation in Each Transfer Mode
Note:
22.3.2
SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the
master clock. SISCR can be specified when the bits TRMD[1:0] in SIMDR are specified as B'10
or B'11.
Rev.1.00 Dec. 13, 2005 Page 804 of 1286
REJ09B0158-0100
Initial value:
Transfer Mode
Slave mode 1
Slave mode 2
Master mode 1
Master mode 2
Bit
15
14
13
R/W:
Bit:
*
Clock Select Register (SISCR)
Bit Name
MSSEL
MSIMM
—
MSSEL MSIMM
The control data method is valid only when the FL bits are specified as B'1xxx. (x: don't
care)
R/W
15
1
R/W
14
1
Master
Master
Master/Slave
Slave
Slave
13
—
R
0
Initial
Value
1
1
0
R/W
12
0
R/W
R/W
R/W
R
R/W
11
0
SIOF_SYNC
Synchronous pulse
Synchronous pulse
Synchronous pulse
L/R
BRPS[4:0]
R/W
10
0
Description
Master Clock Source Selection
The master clock is the clock source input to the baud
rate generator (prescaler).
0: Uses the input clock signal of the SIOF_MCLK pin as
1: Uses peripheral clock (Pck) as the master clock
Master Clock Direct Selection
0: Uses the output clock of the baud rate generator as
1: Uses the master clock itself as the serial clock
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W
the master clock
the serial clock
0
9
R/W
8
0
—
R
7
0
Bit Delay
SYNCDL bit
No
—
R
6
0
—
R
5
0
—
Control Data Method*
Slot position
Secondary FS
Slot position
Not supported
R
4
0
—
R
3
0
R/W
2
0
BRDV[2:0]
R/W
1
0
R/W
0
0