R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 492

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 DDR-SDRAM Interface (DDRIF)
12.7
12.7.1
The DDRIF supports ratios of 5:4 (DDR320) and 1:1 (DDR266) between the frequencies of the
SuperHyway clock (SHck) and DDR clock (DDRck). For details, see section 15, Clock Pulse
Generator (CPG). The maximum operating frequency of the SuperHyway clock is 200 MHz. The
minimum operating frequency depends on the frequency of the DDR-SDRAM clock. Therefore,
see the datasheet for the DDR-SDRAM.
12.7.2
Supply of the clock signal for the DDRIF stops in the following two cases:
• when the SDRAM is in battery backup mode; and
• when the PLL multiplication ratio or bus-clock frequency-division ratio is changed by the
Since the clock signal is not being supplied in the above situations, auto-refreshing does not
proceed. Since the refresh cycle is not being maintained, data in the SDRAM will be lost. To
prevent this, software should place the SDRAM in the self-refresh state before supply of the clock
signal is stopped. For details on making the SDRAM enter and leave the self-refresh mode, see
section 12.5.5 (1), Self-Refresh Mode.
12.7.3
The DDR-SDRAM bank is automatically opened by the DDRIF access (read from or written to).
When the REFA (auto-refresh) command is issued by using the SMS bits in SCR, be sure to close
the bank by using the SMS bits in SCR to issue the PREALL command. The same operation is
necessary when the SCR register setting is used to issue a REFA command for refreshing all rows
in the memory before starting up auto-refresh operations.
12.7.4
The DDRIF only supports memory in which the number of cycles (tRAP) required from issuing an
ACT command to issuing a read with auto-precharge or write with auto-precharge command and
the number of cycles (tRCD) required from issuing an ACT command to issuing a read or write
command are the same. If the two numbers differ, the SDRAM should be accessed in bank open
mode.
Rev.1.00 Dec. 13, 2005 Page 440 of 1286
REJ09B0158-0100
frequency change register (FRQCR) of the CPG.
Usage Notes
Operating Frequency
Stopping Clock
Using SCR to Issue REFA Command (Outside the Initialization Sequence)
Timing of Connected SDRAM