R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 326

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Interrupt Controller (INTC)
Procedure for Using the User Interrupt Mask Level Register
Interrupts with priority levels less than or equal to the value set in USERIMASK are disabled.
This function can be used to disable less urgent interrupts during the execution of urgent tasks that
run in user mode, e.g. device drivers, and thus reduce times until completion for such tasks.
USERIMASK is allocated to a different 64-Kbyte page than that to which the other INTC registers
are allocated. When accessing this register in user mode, translate the address through the MMU.
In a system with a multitasking OS, the memory-protection functions of the MMU must be used to
control which processes have access to USERIMASK. When terminating a task or switching to
another task, be sure to clear USERIMASK to 0 beforehand. If the UIMASK bits are erroneously
left set at a value other than zero, interrupts which are not higher in priority than the UIMASK
level remain disabled, and operation may be incorrect (for example, the OS might be unable to
switch between tasks).
An example of the usage procedure is given below.
1. Classify interrupts as A or B, described below, and set the priority of A-type interrupts higher
2. Make the MMU settings so that the address space which contains USERIMASK can only be
3. Branch to the device driver.
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REJ09B0158-0100
Bit
31 to 24 WKEY
23 to 8
7 to 4
3 to 0
than that of the B-priority interrupts.
A. Interrupts to be accepted by device drivers (interrupts for use by the operating system: a
B. Interrupts to be disabled during the execution of device drivers
accessed by the device driver for which interrupts should be disabled.
timer interrupt etc.)
Name
—
UIMASK
—
Initial
Value
H'00
All 0
H'0
All 0
R/W
R/W
R
R/W
R
Description
When writing a value to bits 7 to 4, always write H'A5
here. These bits are always read as 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Interrupt Mask Level
Mask interrupts with priority levels lower than the level
set in the UIMASK bits.
Reserved
These bits are always read as 0. The write value
should always be 0.