R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 949
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 949 of 1342
- Download datasheet (7Mb)
24.3.15 Data Timeout Register (DTOUTR)
DTOUTR specifies the period to generate a data timeout. The 16-bit counter (DTOUTC) and a
prescaler, to which the peripheral bus does not have access, count the peripheral clock to monitor
the data timeout. The prescaler always counts the peripheral clock, and outputs a count pulse for
every 10,000 peripheral clock cycles. The initial value of DTOUTC is 0, and DTOUTC starts
counting the prescaler output from the start of the command sequence. DTOUTC is cleared when
the command sequence has ended, or when the command sequence has been aborted by setting the
CMDOFF bit to 1, after which the DTOUTC stops counting the prescaler output.
When the command sequence does not end, DTOUTC continues counting the prescaler output,
and enters the data timeout error states when the number of prescaler outputs reaches the number
specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1
is set. As DTOUTC continues counting prescaler output, the DTERI flag setting condition is
repeatedly generated. To perform data timeout error handling, the command sequence should be
aborted by setting the CMDOFF bit to 1, and then the DTERI flag should be cleared to prevent
extra-interrupt generation.
For a command with data busy status, data timeout cannot be monitored since the command
sequence is terminated before entering the data busy state. Timeout in the data busy state should
be monitored by firmware.
Initial value:
Bit
15 to 0
R/W:
Bit:
Bit Name
DTOUTR
R/W
15
1
R/W
14
1
R/W
13
1
Initial
Value
All 1
R/W
12
1
R/W
11
R/W
R/W
1
R/W
10
1
Description
Data Timeout Time/10,000
Data timeout time: Peripheral clock cycle × DTOUTR
setting value × 10,000.
R/W
9
1
R/W
8
1
DTOUTR
R/W
Section 24 Multimedia Card Interface (MMCIF)
7
1
Rev.1.00 Dec. 13, 2005 Page 897 of 1286
R/W
6
1
R/W
5
1
R/W
4
1
R/W R/W
3
1
REJ09B0158-0100
2
1
R/W
1
1
R/W
0
1
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