R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 821

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21.4
21.4.1
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is
achieved character by character and in synchronous mode, in which synchronization is achieved
with clock pulses. For details on asynchronous mode, see section 21.4.2, Operation in
Asynchronous Mode.
64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead, and enabling fast and continuous communication to be performed.
SCIF0_RTS and SCIF0_CTS signals are also provided as modem control signals (channel 0 only).
The serial transfer format is selected using SCSMR, as shown in table 21.4. The SCIF clock
source is determined by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits
in SCSCR, as shown in table 21.5.
Note: Since the operations are the same in each channel except for the modem control, the
Asynchronous Mode:
• Data length: Choice of 7 or 8 bits
• LSB first for data transmission/reception
• Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters
• Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receive-
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Choice of internal (peripheral clock: Pck) or external clock (SCIF_SCK input clock) as SCIF
determines the transfer format and character length)
data-ready state, and breaks, during reception
clock source
When internal clock is selected: The SCIF operates on the baud rate generator clock and can
output a clock with frequency of 16 times the bit rate from SCIF_SCK pin.
When external clock is selected: A clock with a frequency of 16 times the bit rate must be
input (the on-chip baud rate generator is not used).
channel number n (n = 0, 1) is omitted in the description below.
Operation
Overview
Section 21 Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Dec. 13, 2005 Page 769 of 1286
REJ09B0158-0100