R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 212

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 Memory Management Unit (MMU)
7.2.5
The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should
be performed by a program in the P1 or P2 area.
After MMUCR has been updated, execute one of the following three methods before an access
(including an instruction fetch) to the P0, P3, U0, or store queue area is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be the P0,
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the R2 bit in IRMCR is 0 (initial value) before updating MMUCR, the specific instruction
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
MMUCR contents can be changed by software. However, the LRUI and URC bits may also be
updated by hardware.
Initial value:
Initial value:
Rev.1.00 Dec. 13, 2005 Page 160 of 1286
REJ09B0158-0100
P3, or U0 area.
does not need to be executed. However, note that the CPU processing performance will be
lowered because the instruction fetch is performed again for the next instruction after
MMUCR has been updated.
R/W:
R/W:
Bit:
Bit:
MMU Control Register (MMUCR)
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
LRUI
URC
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
26
10
0
0
SQMD SV
R/W
25
R
0
9
0
R/W
24
R
0
0
8
R/W
23
0
R
0
7
R/W
22
0
R
0
6
R/W
21
0
R
0
5
URB
R/W
20
0
R
0
4
R/W
19
0
R
0
3
R/W
R/W
18
TI
0
2
0
17
R
0
1
0
R
R/W
AT
16
R
0
0
0

Related parts for R8A77800ANBGAV