R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 897
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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22.4.9
Examples of the SIOF serial transmission and reception are shown in figure 22.13 to figure 22.19.
8-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for
transmit and receive data, an frame length = 8 bits
8-bit Monaural Data (2): Synchronous pulse method, falling edge sampling, slot No.0 used for
transmit and receive data, and frame length = 16 bits
SIOF_RXD
SIOF_SCK
SIOF_SYNC
SIOF_TXD
Transmit and Receive Timing
Figure 22.13 Transmit and Receive Timing (8-Bit Monaural Data (1))
Figure 22.14 Transmit and Receive Timing (8-Bit Monaural Data (2))
Specifications:
SIOF_RXD
SIOF_SCK
SIOF_SYNC
SIOF_TXD
Specifications:
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 0,
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 0,
1-bit delay
L-channel data
Slot No.0
1-bit delay
L-channel data
Slot No.0
1 frame
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000,
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000,
1 frame
Slot No.1
FL[3:0] = 0000 (frame length: 8 bits)
TDRE = 0,
RDRE = 0,
CD1E = 0,
FL[3:0] = 0100 (frame length: 16 bits)
TDRE = 0,
RDRE = 0,
CD1E = 0,
Rev.1.00 Dec. 13, 2005 Page 845 of 1286
Section 22 Serial I/O with FIFO (SIOF)
TDRA[3:0] = 0000,
RDRA[3:0] = 0000,
CD1A[3:0] = 0000
TDRA[3:0] = 0000,
RDRA[3:0] = 0000,
CD1A[3:0] = 0000
REJ09B0158-0100
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