R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 388

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 Local Bus State Controller (LBSC)
11.4.3
CSnBCR are 32-bit readable/writable registers that specify the bus width for area n (n = 0 to 2 and
4 to 6), numbers of wait, setup, and hold cycles to be inserted, burst length, and memory types.
Some types of memory continue to drive the data bus immediately after the read signal is
inactivated. Therefore, a data bus collision may occur when there is consecutive memory access to
different areas or writing to a memory immediately after reading. This LSI automatically inserts
the number of idle cycles set by CSnBCR to prevent data bus collision.
CSnBCR is initialized to H'7777 7770 by a power-on reset, but is not initialized by a manual reset.
Do not access external memory space other than area 0 until the CSnBCR initialization is
completed.
Rev.1.00 Dec. 13, 2005 Page 336 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
6 to 0
R/W:
R/W:
Bit:
Bit:
CSn Bus Control Register (CSnBCR)
Bit Name
ASYNC[6:0]
Note: * Bits SZ and MPX in CS0BCR are read-only.
31
15


R
R
0
0
R/W
R/W
30
14
1
1
IWRRS
IWW
R/W
R/W
29
13
1
1
Initial
Value
All 0
R/W
R/W
28
12
1
1
R/W
R/W
R/W
27

11
R
0
0
BST
R/W
R/W
26
10
1
1
Description
Asynchronous Input
Enable asynchronous input to the corresponding pins.
0: Input signals to the corresponding pins must be
1: Input signals to the corresponding pins can be
ASYNC[6]: DREQ3
ASYNC[5]: DREQ2
ASYNC[4]: DREQ1
ASYNC[3]: DREQ0
ASYNC[2]: IOIS16
ASYNC[1]: BREQ
ASYNC[0]: RDY
IWRWD
R/W*
R/W
25
1
9
1
synchronized with CLKOUT
asynchronous to CLKOUT
SZ
R/W*
R/W
24
1
8
1
RDSPL
R/W
23

R
0
7
0
R/W
R/W
22
1
6
1
IWRWS
R/W
R/W
BW
21
1
5
1
R/W
R/W
20
1
4
1
R/W*
MPX
19

R
0
3
0
R/W
R/W
18
1
2
0
IWRRD
TYPE
R/W
R/W
17
1
1
0
R/W
R/W
16
1
0
0