R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 317

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note: ‘H’ and ‘L’ indicate high- and low-level input on the corresponding IRQ/IRL pin. For the
Bit
11
10
9
8
7
6
5
4
3
2
1
0
relationship between the input signal level and the priority level, refer to table 10.11.
Name
IM111
IM110
IM109
IM108
IM107
IM106
IM105
IM104
IM103
IM102
IM101
—
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Sets masking of interrupt-
request generation by IRL7
to IRL4 = LHLL (H'4).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = LHLH (H'5).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = LHHL (H'6).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = LHHH (H'7).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = HLLL (H'8).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = HLLH (H'9).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = HLHL (H'A).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = HLHH (H'B).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = HHLL (H'C).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = HHLH (H'D).
Sets masking of interrupt-
request generation by IRL7
to IRL4 = HHHL (H'E).
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev.1.00 Dec. 13, 2005 Page 265 of 1286
Section 10 Interrupt Controller (INTC)
[When reading]
0: The interrupt is
1: The interrupt is
[When wswriting]
0: No effect
1: Masks the interrupt
Initial value: 0
acceptable.
masked.
REJ09B0158-0100