R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 887

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Control by Secondary FS (Slave Mode 2): The CODEC normally outputs the SIOF_SYNC
signal as synchronization pulse (FS). In this method, the CODEC outputs the secondary FS
specific to the control data transfer after 1/2 frame time has been passed (not the normal FS output
timing) to transmit or receive control data. This method is valid for SIOF slave mode. The
following summarizes the control data interface procedure by the secondary FS.
• Transmit normal transmit data of LSB = 0 (the SIOF forcibly clears 0).
• To execute control data transmission, send transmit data of LSB = 1 (the SIOF forcibly set to 1
• The CODEC outputs the secondary FS.
• The SIOF transmits or receives (stores in SIRCR) control data (data specified by SITCR)
Figure 22.8 shows an example of the control data interface timing by the secondary FS.
SIOF_RXD
SIOF_SCK
SIOF_SYNC
SIOF_TXD
by writing SITCR).
synchronously with the secondary FS.
Specifications: TRMD[1:0] = 01,
Normal FS
L-channel
No.0
data
Slot
Figure 22.8 Control Data Interface (Secondary FS)
TDLE = 1,
RDLE = 1,
CD0E = 1,
LSB=1 (Secondary FS request)
1/2
frame
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000,
1 frame
Secondary FS
channel 0
Control
No.0
Slot
FL[3:0] = 1110 (Frame length: 128 bits),
TDRE = 0,
RDRE = 0,
CD1E = 0,
Rev.1.00 Dec. 13, 2005 Page 835 of 1286
Section 22 Serial I/O with FIFO (SIOF)
1/2
TDRA[3:0] = 0000,
RDRA[3:0] = 0000,
CD1A[3:0] = 0000
frame
REJ09B0158-0100
Normal FS