R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 510

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 PCI Controller (PCIC)
Rev.1.00 Dec. 13, 2005 Page 458 of 1286
REJ09B0158-0100
Bit
6
5
4
3
2
1
0
Bit Name
PER
VGAPS
MWIE
SC
BM
MS
IOS
Initial
Value
0
0
0
0
0
0
0
R/W
SH: R/W
PCI: R/W
SH: R
PCI: R
SH: R
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R/W
SH: R/W
PCI: R/W
SH: R/W
PCI: R/W
Description
Parity Error
Controls the device's response when the PCIC detects
a parity error or receives a parity error. When this bit is
set to 1, the PERR signal is asserted.
0: No response parity error
1: Response parity error
VGA Palette Snoop Control
0: VGA compatible device
1: Palette register write is not supported (not
supported)
PCI Memory Write and Invalidate Control
Controls issuance of a memory write and invalidate
command in a master access.
0: Memory write is used
1: Memory write and invalidate command is executable
PCI Special Cycles
Indicates whether or not to support the special cycle
operations in a target access.
0: Special cycles ignored
1: Special cycles monitored (not supported)
PCI Bus Master Control
Controls a bus master.
0: Bus master function disabled
1: Bus master function enabled
PCI Memory Space Control
Controls accesses to memory space of this LSI. When
this bit is cleared to 0, a memory transfer to the PCIC is
terminated with a master abort.
0: Does not respond to memory space accesses
1: Respond to memory space accesses
PCI I/O Space
Controls accesses to I/O space of this LSI. When this
bit is cleared to 0, a I/O transfer to the PCIC is
terminated with a master abort.
0: Does not respond to I/O space accesses
1: Respond to I/O space accesses
(not supported)