R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 97

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 2.2
Floating-Point Communication Register (FPUL) (32 bits, Initial Value = Undefined):
Information is transferred between the FPU and CPU via FPUL.
Field Name
Cause
Enable
Flag
<Little endian>
<Big endian>
Floating-point register
Floating-point register
FPU exception
FPU exception
cause field
enable field
FPU exception flag
field
Bit Allocation for FPU Exception Handling
Memory area
Memory area
Figure 2.5 Relationship between SZ bit and Endian
Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used.
8n
4n+3
63
63
63
63
63
63
2. The bit-location of DR register is used for double precision format when PR = 1.
FR (2i)
FR (2i)
(In the case of (2), it is used when PR is changed from 0 to 1.)
FPU
Error (E)
Bit 17
None
None
8n+3
(1) SZ = 0
DR (2i)
32 31
DR (2i)
4n
32 31
4m+3
8n+4
FR (2i+1)
FR (2i+1)
Invalid
Operation (V)
Bit 16
Bit 11
Bit 6
8n+7
*1, *2
4m
0
0
0
0
0
0
8n+3
63
63
63
FR (2i)
(2) SZ = 1, PR = 0
Division
by Zero (Z)
Bit 15
Bit 10
Bit 5
DR (2i)
8n
32 31
8n+7
FR (2i+1)
Rev.1.00 Dec. 13, 2005 Page 45 of 1286
8n+4
*2
0
0
0
Overflow
(O)
Bit 14
Bit 9
Bit 4
8n+7
63
Section 2 Programming Model
63
63
FR (2i)
(3) SZ = 1, PR = 1
8n+4
Underflow
(U)
Bit 13
Bit 8
Bit 3
DR (2i)
32 31
8n+3
FR (2i+1)
REJ09B0158-0100
8n
0
0
0
Inexact
(I)
Bit 12
Bit 7
Bit 2

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