R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 149

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.1
Exception handling processing is handled by a special routine which is executed by a reset,
general exception handling, or interrupt. For example, if the executing instruction ends
abnormally, appropriate action must be taken in order to return to the original program sequence,
or report the abnormality before terminating the processing. The process of generating an
exception handling request in response to abnormal termination, and passing control to a user-
written exception handling routine, in order to support such functions, is given the generic name of
exception handling.
The exception handling in this LSI is of three kinds: resets, general exceptions, and interrupts.
5.2
Table 5.1 lists the configuration of registers related exception handling.
Table 5.1
Note:
Table 5.2
Register Name
TRAPA exception register
Exception event register
Interrupt event register
Register Name
TRAPA exception register
Exception event register
Interrupt event register
*
Summary of Exception Handling
Register Descriptions
P4 is the address when virtual address space P4 area is used. Area 7 is the address
when physical address space area 7 is accessed by using the TLB.
Register Configuration
States of Register in Each Operating Mode
Section 5 Exception Handling
Abbreviation
TRA
EXPEVT
INTEVT
Abbreviation
TRA
EXPEVT
INTEVT
Power-on Reset
Undefined
H'0000 0000
Undefined
R/W
R/W
R/W
R/W
P4 Address*
H'FF00 0020
H'FF00 0024
H'FF00 0028
Rev.1.00 Dec. 13, 2005 Page 97 of 1286
Manual Reset
Undefined
H'0000 0020
Undefined
Area 7 Address*
H'1F00 0020
H'1F00 0024
H'1F00 0028
Section 5 Exception Handling
REJ09B0158-0100
Sleep
Retained
Retained
Retained
Access
Size
32
32
32