R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 891

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Reception in Master Mode: Figure 22.10 shows an example of settings and operation for master
mode reception.
No.
5
6
2
4
7
8
1
3
Store SIOFRXD receive data in SIRDR
SIRDAR, SICDAR, and SIFCTR
synchronously with SIOF_SYNC
Clear the RXE bit in SICTR to 0
Set the SCKE bit in SICTR to 1
Set the FSE and RXE bits
Start SIOFSCK output
Set SIMDR, SISCR,
Figure 22.10 Example of Receive Operation in Master Mode
in SICTR to 1
RDREQ = 1?
Read SIRDR
Flow Chart
Transfer
ended?
Start
End
Yes
Yes
No
No
Set operating mode, serial clock,
slot positions for receive data,
slot position for control data, and
FIFO request threshold value
Set operation start for baud rate
generator
Set the start for frame synchronous
signal output and enable
reception
Read receive data
Set to disable reception
SIOF Settings
Rev.1.00 Dec. 13, 2005 Page 839 of 1286
Section 22 Serial I/O with FIFO (SIOF)
Output serial clock
Output frame synchronous
signal
Issue receive transfer
request according to the
receive FIFO threshold
value
Reception
End reception
SIOF Operation
REJ09B0158-0100