R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 627

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
19
Bit Name
HE
Initial
Value
0
R/W
R/(W)* Half End Flag
Descriptions
After HIE (bit 18) is set to 1 and the number of transfers
become half of TCR (1 bit shift to right) which is set
before transfer starts, HE becomes 1.
This bit is set to 1 when the TCR value is equal to any
of the following:
•
•
•
The HE bit is not set when transfers are ended by an
NMI interrupt or address error, or by clearing the DE bit
or the DME bit in DMAOR before the number of
transfers is decreased to half of the TCR value set
preceding the transfer. The HE bit is kept set when the
transfer ends by an NMI interrupt or address error, or
clearing the DE bit (bit 0) or the DME bit in DMAOR
after the HE bit is set to 1. To clear the HE bit, write 0
after reading 1 in the HE bit. This bit is valid only in
CHCR0 to CHCR3 and CHCR6 to CHCR9.
0: During the DMA transfer or DMA transfer has been
[Clearing condition]
Writing 0 after HE = 1 is read.
1: TCR = (TCR set before transfer)/2
interrupted
TCR > (TCR set before transfer)/2
(TCR set before transfer)/2 (TCR: even number)
(TCR set before transfer - 1)/2 (TCR: odd number)
8,388,608 (H'0080 0000) (TCR: maximum number
H'0000 0000)
Section 14 Direct Memory Access Controller (DMAC)
Rev.1.00 Dec. 13, 2005 Page 575 of 1286
REJ09B0158-0100