R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 932

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 24 Multimedia Card Interface (MMCIF)
24.3.6
The INTSTR registers enable or disable MMCIF interrupts FSTAT, TRAN, ERR and FRDY.
• INTSTR0
Rev.1.00 Dec. 13, 2005 Page 880 of 1286
REJ09B0158-0100
Bit
7
6
Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2)
Bit Name
FEI
FFI
Initial value:
Initial
Value
0
0
R/W:
Bit:
R/W
FEI
0
7
R/W
R/W
R/W
R/W
FFI
6
0
Description
FIFO Empty Interrupt Flag
0: No interrupt
[Clearing condition]
Write 0 after reading FEI = 1.
(Writing 1 is invalid)
1: Interrupt requested
[Setting condition]
When FIFO becomes empty while FEIE =
1 and data is being transmitted
(when the FIFO_EMPTY bit in CSTR is
set)
FIFO Full Interrupt Flag
0: No interrupt
[Clearing condition]
Write 0 after reading FFI = 1.
(Writing 1 is invalid)
1: Interrupt requested
[Setting condition]
When FIFO becomes full while FFIE = 1
and data is being received
(when the FIFO_FULL bit in CSTR is set)
DRPI
R/W
5
0
DTI
R/W
4
0
CRPI CMDI DBSYI
R/W
3
0
R/W
2
0
R/W
1
0
R/W
BTI
0
0
Interrupt
output
FSTAT
FSTAT