R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 367
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 367 of 1342
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The local bus state controller (LBSC) divides the external memory space and outputs control
signals corresponding to the specifications of various types of memory and bus interfaces. The
LBSC enables the connection of SRAM or ROM, etc., to this LSI. It also supports the PCMCIA
interface protocol, which is used to implement simplified system design and high-speed data
transfers in a compact system.
11.1
The LBSC has the following features.
• Controls six areas, areas 0 to 2 and 4 to 6, of an external memory space divided into seven
• SRAM interface
• Burst ROM interface
areas.
Maximum 64 Mbytes for each of areas 0 to 2 and 4 to 6
Bus width of each area can be controlled through register settings (except area 0, which is
Wait-cycle insertion by the RDY pin
Wait-cycle insertion can be controlled by a program
Types of memory are specifiable for connection to each area
Output of the control signals of memory to each area
Automatic wait cycle insertion to prevent data bus collisions on consecutive memory
Insertion of cycles to ensure the setup time and hold time to the write strobe on a write
Wait-cycle insertion can be controlled by a program
Insertion of the wait cycle through the RDY pin
Wait-cycle insertion can be controlled by a program
Burst length specified by the register
controlled by the external pin setting)
accesses
cycle enables connection to low-speed memory
Connectable areas : 0 to 2 and 4 to 6
Settable bus widths: 32, 16, and 8 bits
Connectable areas: 0 to 2 and 4 to 6
Settable bus widths: 32, 16, and 8 bits
Features
Section 11 Local Bus State Controller (LBSC)
Section 11 Local Bus State Controller (LBSC)
Rev.1.00 Dec. 13, 2005 Page 315 of 1286
REJ09B0158-0100
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