R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 552

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 PCI Controller (PCIC)
(11) PCI Arbiter Interrupt Mask Register (PCIAINTM)
This register is the mask register for PCIAINT.
Rev.1.00 Dec. 13, 2005 Page 500 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
0
Bit
31 to 14 
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
Bit:
Bit:
Bit Name
Bit Name
WDPEI
31
15
—
—
R
R
R
R
0
0
30
14
—
—
R
R
R
R
0
0
MBIM
R/W
Initial
Value
All 0
Initial
Value
0
29
13
—
R
R
R
0
0
R/W
TBT
OIM
28
12
—
R
R
R
0
0
R/W
SH: R
PCI: R
R/W
SH: R/WC
PCI: R
R/W
MBT
OIM
27
—
11
R
R
R
0
0
26
10
—
—
R
R
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Description
Write Parity Error Interrupt
The PERR assertion is detected during a data write
when a device other than the PCIC functions as a
bus master.
0: Write parity error interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Write parity error interrupt occurs
[Set condition]
When a write parity error interrupt is detected by the
PERR assertion.
25
—
—
R
R
R
R
9
0
0
24
—
—
R
R
R
R
0
8
0
23
—
—
R
R
R
R
0
7
0
22
—
—
R
R
R
R
0
6
0
21
—
—
R
R
R
R
0
5
0
20
—
—
R
R
R
R
0
4
0
TAIM
R/W
19
—
R
R
R
0
3
0
MAIM
R/W
18
—
R
R
R
0
2
0
R/W
RDP
EIM
17
—
R
R
R
0
1
0
WDP
R/W
EIM
16
—
R
R
R
0
0
0