PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 225

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 18-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
FIGURE 18-19:
TABLE 18-3:
 2010 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
2:
16 MHz
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
F
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
F
OSC
CY
2
must be at least 16 MHz for I
C™ interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE w/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C Master mode, the BRG is
SSPM<3:0>
SCL
32 MHz
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
CY
SSPM<3:0>
CY
* 2
) on the
Reload
Control
2
C bus operation at this speed.
Preliminary
CLKO
Reload
PIC18F87J72 FAMILY
Table 18-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
18.4.7.1
When the device is operating in one of the
power-managed modes, the clock source to the BRG
may change frequency or even stop, depending on the
mode and clock source selected. Switching to a Run or
Idle mode from either the secondary clock or internal
oscillator is likely to change the clock rate to the BRG.
In Sleep mode, the BRG will not be clocked at all.
BRG Down Counter
2
Note:
C specification (which applies to rates greater than
SSPADD<6:0>
BRG Value
0Ch
1Fh
03h
18h
63h
09h
27h
02h
09h
A BRG value of 00h is not supported.
Baud Rate Generation in
Power-Managed Modes
F
OSC
(2 Rollovers of BRG)
/4
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
DS39979A-page 225
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(2)
(2)
(2)