PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 474

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
DS39979A-page 474
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep .................... 252
Baud Rate Generator with Clock Arbitration ............. 226
BRG Overflow Sequence .......................................... 247
BRG Reset Due to SDA Arbitration During
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision During Start Condition
Bus Collision for Transmit and Acknowledge............ 233
Capture/Compare/PWM............................................ 411
CLKO and I/O ........................................................... 408
Clock Synchronization .............................................. 219
Clock/Instruction Cycle ............................................... 60
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ...................... 412
Example SPI Master Mode (CKE = 1) ...................... 413
Example SPI Slave Mode (CKE = 0) ........................ 414
Example SPI Slave Mode (CKE = 1) ........................ 415
External Clock ........................................................... 406
Fail-Safe Clock Monitor (FSCM) ............................... 330
First Start Bit Timing ................................................. 227
I
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I
LCD Interrupt in Quarter Duty Cycle Drive................ 190
LCD Sleep Entry/Exit When SLPEN = 1 or
MSSP I
MSSP I
PWM Output ............................................................. 163
Repeated Start Condition.......................................... 228
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................. 253
Slave Synchronization .............................................. 201
Slow Rise Time (MCLR Tied to V
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................. 417
C Bus Start/Stop Bits.............................................. 416
C Master Mode (7 or 10-Bit Transmission) ............ 230
C Master Mode (7-Bit Reception) ........................... 231
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) ........... 215
C Slave Mode (10-Bit Reception, SEN = 1) ........... 221
C Slave Mode (10-Bit Transmission)...................... 217
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............. 212
C Slave Mode (7-Bit Reception, SEN = 1) ............. 220
C Slave Mode (7-Bit Transmission)........................ 214
C Slave Mode General Call Address Sequence
C Stop Condition Receive or Transmit Mode ......... 232
Normal Operation.............................................. 252
Start Condition .................................................. 235
Condition (Case 1) ............................................ 236
Condition (Case 2) ............................................ 236
(SCL = 0) .......................................................... 235
(Case 1) ............................................................ 237
(Case 2) ............................................................ 237
(SDA Only)........................................................ 234
(Master/Slave)................................................... 420
(Master/Slave)................................................... 420
ADMSK = 01001) .............................................. 216
ADMSK = 01011) .............................................. 213
(7 or 10-Bit Addressing Mode) .......................... 222
CS1:CS0 = 00 ................................................... 191
Timer (OST) and Power-up Timer (PWRT) ...... 409
V
DD
2
2
C Bus Data .................................................. 418
C Bus Start/Stop Bits .................................. 418
Rise > T
PWRT
) ............................................. 47
DD
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Preliminary
Timing Diagrams and Specifications
SPI Mode (Master Mode).......................................... 200
SPI Mode (Slave Mode, CKE = 0) ............................ 202
SPI Mode (Slave Mode, CKE = 1) ............................ 202
Synchronous Reception (Master Mode,
Synchronous Transmission .............................. 254, 268
Synchronous Transmission
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer Pulse Generation............................................ 154
Timer0 and Timer1 External Clock ........................... 410
Transition for Entry to Idle Mode................................. 40
Transition for Entry to SEC_RUN Mode ..................... 37
Transition for Entry to Sleep Mode ............................. 39
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode............... 40
Transition for Wake From Sleep (HSPLL) .................. 39
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ...................................... 38
Type-A in 1/2 MUX, 1/2 Bias Drive ........................... 180
Type-A in 1/2 MUX, 1/3 Bias Drive ........................... 182
Type-A in 1/3 MUX, 1/2 Bias Drive ........................... 184
Type-A in 1/3 MUX, 1/3 Bias Drive ........................... 186
Type-A in 1/4 MUX, 1/3 Bias Drive ........................... 188
Type-A/Type-B in Static Drive .................................. 179
Type-B in 1/2 MUX, 1/2 Bias Drive ........................... 181
Type-B in 1/2 MUX, 1/3 Bias Drive ........................... 183
Type-B in 1/3 MUX, 1/2 Bias Drive ........................... 185
Type-B in 1/3 MUX, 1/3 Bias Drive ........................... 187
Type-B in 1/4 MUX, 1/3 Bias Drive ........................... 189
A/D Conversion Requirements ................................. 422
Capture/Compare/PWM Requirements .................... 411
CLKO and I/O Requirements.................................... 408
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements ................................... 406
I
I
Internal RC Accuracy (INTOSC and INTRC)............ 407
MSSP I
MSSP I
PLL Clock ................................................................. 407
2
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C Bus Data Requirements (Slave Mode) ............... 417
C Bus Start/Stop Bits Requirements |(Slave Mode).....
SREN) ...................................................... 256, 270
(Through TXEN) ....................................... 255, 269
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTRC to HSPLL)............................................ 328
PRI_RUN Mode.................................................. 38
PRI_RUN Mode (HSPLL) ................................... 37
Requirements ................................................... 420
Requirements ................................................... 420
(Master Mode, CKE = 0)................................... 412
(Master Mode, CKE = 1)................................... 413
(Slave Mode, CKE = 0)..................................... 414
(CKE = 1).......................................................... 415
416
2
2
C Bus Data Requirements .......................... 419
C Bus Start/Stop Bits Requirements........... 418
 2010 Microchip Technology Inc.
DD
, V
DD
DD
DD
), Case 1 ....................... 46
), Case 2 ....................... 47
Rise T
PWRT
) ............... 46