PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 473

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

RTCEN Bit Write ............................................................... 149
S
SCK................................................................................... 195
SDI .................................................................................... 195
SDO .................................................................................. 195
SEC_IDLE Mode................................................................. 40
SEC_RUN Mode ................................................................. 36
Serial Clock, SCK ............................................................. 195
Serial Data In (SDI) ........................................................... 195
Serial Data Out (SDO) ...................................................... 195
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................. 368
Slave Select (SS) .............................................................. 195
SLEEP .............................................................................. 369
Software Simulator (MPLAB SIM)..................................... 387
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ............................................ 319
SPI Mode (MSSP)
SS ..................................................................................... 195
SSPOV.............................................................................. 229
SSPOV Status Flag .......................................................... 229
SSPSTAT Register
Stack Full/Underflow Resets ............................................... 59
SUBFSR ........................................................................... 380
SUBFWB........................................................................... 369
SUBLW ............................................................................. 370
SUBULNK ......................................................................... 380
SUBWF ............................................................................. 370
SUBWFB........................................................................... 371
SWAPF ............................................................................. 371
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Operation
Register Interface...................................................... 149
Register Maps........................................................... 155
Reset......................................................................... 154
Sleep Mode............................................................... 154
Value Registers (RTCVAL) ....................................... 144
Associated Registers ................................................ 203
Bus Mode Compatibility ............................................ 203
Effects of a Reset...................................................... 203
Enabling SPI I/O ....................................................... 199
Master Mode ............................................................. 200
Operation .................................................................. 198
Operation in Power-Managed Modes ....................... 203
Serial Clock............................................................... 195
Serial Data In ............................................................ 195
Serial Data Out ......................................................... 195
Slave Mode ............................................................... 201
Slave Select .............................................................. 195
Slave Select Synchronization ................................... 201
SPI Clock .................................................................. 200
Typical Connection ................................................... 199
R/W Bit.............................................................. 209, 211
Calibration......................................................... 152
Clock Source .................................................... 150
Digit Carry Rules............................................... 150
General Functionality ........................................ 151
Leap Year ......................................................... 151
Register Mapping.............................................. 151
Safety Window for Register Reads
Write Lock ......................................................... 151
Device ............................................................... 154
Power-on Reset (POR) ..................................... 154
ALRMVAL ................................................. 152
RTCVAL.................................................... 151
and Writes................................................. 151
Preliminary
PIC18F87J72 FAMILY
T
Table Pointer Operations (table)......................................... 80
Table Reads/Table Writes .................................................. 59
TBLRD .............................................................................. 372
TBLWT ............................................................................. 373
Timer0 .............................................................................. 123
Timer1 .............................................................................. 127
Timer2 .............................................................................. 133
Timer3 .............................................................................. 135
Timing Diagrams
Associated Registers................................................ 125
Clock Source Select (T0CS Bit) ............................... 124
Operation.................................................................. 124
Overflow Interrupt ..................................................... 125
Prescaler .................................................................. 125
Prescaler Assignment (PSA Bit)............................... 125
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode............................. 124
Source Edge Select (T0SE Bit) ................................ 124
16-Bit Read/Write Mode ........................................... 129
Associated Registers................................................ 131
Interrupt .................................................................... 130
Operation.................................................................. 128
Oscillator........................................................... 127, 129
Oscillator, as Secondary Clock................................... 27
Resetting, Using the CCP Special
TMR1H Register....................................................... 127
TMR1L Register ....................................................... 127
Use as a Clock Source ............................................. 129
Use as a Real-Time Clock ........................................ 130
Associated Registers................................................ 134
Interrupt .................................................................... 134
Operation.................................................................. 133
Output....................................................................... 134
PR2 Register ............................................................ 163
TMR2 to PR2 Match Interrupt................................... 163
16-Bit Read/Write Mode ........................................... 137
Associated Registers................................................ 137
Operation.................................................................. 136
Oscillator........................................................... 135, 137
Overflow Interrupt ..................................................... 137
Special Event Trigger (CCP) .................................... 137
TMR3H Register....................................................... 135
TMR3L Register ....................................................... 135
A/D Conversion ........................................................ 422
Acknowledge Sequence ........................................... 232
AFE Continuous Read.............................................. 452
AFE Data Ready Behavior ....................................... 455
AFE Data Ready Pulse............................................. 427
AFE Read/Write (SPI Mode 0,0) .............................. 451
AFE Read/Write (SPI Mode 1,1) .............................. 450
AFE Recommended Configuration Sequence.......... 453
AFE Serial Input ....................................................... 427
AFE Serial Output..................................................... 427
AFE Specific Diagrams............................................. 428
Asynchronous Reception.................................. 251, 267
Asynchronous Transmission ............................ 249, 265
Asynchronous Transmission
Automatic Baud Rate Calculation............................. 247
Switching Assignment ...................................... 125
Layout Considerations...................................... 130
Event Trigger .................................................... 130
(Back to Back) .......................................... 249, 265
DS39979A-page 473