PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 284

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
22.1
While it is convenient to think of the dual-channel AFE
as a high-precision ADC, there are actually many more
components involved. The main components are
described below. The dual-channel AFE reference
provides more in-depth information on each.
22.1.1
Each Delta-Sigma ADC is an oversampling converter
that incorporates a built-in modulator which is digitizing
the quantity of charge integrated by the modulator loop.
The quantizer is the block that is performing the
analog-to-digital conversion. The quantizer is typically
1-bit, or a simple comparator, which helps to maintain
the linearity performance of the ADC (the DAC
structure is, in this case, inherently linear).
Multi-bit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR which leads to better SNR
figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADCs.
The 5-level quantizer is a Flash ADC composed of
4 comparators arranged with equally spaced thresholds
and a thermometer coding. The AFE also includes pro-
prietary 5-level DAC architecture that is inherently linear
for improved THD figures.
The resulting channel data is either a 16-bit or 24-bit
word, presented in 23-bit or 15-bit plus sign, two’s
complement format and is MSb (left) justified.
22.1.2
The analog inputs can be connected directly to current
and voltage transducers. Each input pin is protected by
specialized ESD structures that are certified to pass
7 kV HBM and 400V MM contact charge. These
structures allow bipolar ±6V continuous voltage with
respect to SAV
the risk of permanent damage.
22.1.3
The two Programmable Gain Amplifiers (PGAs) reside
at the front-end of each Delta-Sigma ADC. They have
two functions: translate the common-mode of the input
from SAVss to an internal level between SAV
SAV
translation of the common-mode does not change the
differential signal, but recenters the common-mode so
that the input signal can be properly amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma
modulator must not be exceeded.
DS39979A-page 284
DD
, and amplify the input differential signal. The
Functional Overview
DELTA-SIGMA ADC
ARCHITECTURE
ANALOG INPUTS (CHn+/-)
PROGRAMMABLE GAIN
AMPLIFIERS (PGA)
SS
, to be present at their inputs without
SS
and
Preliminary
22.1.4
Both ADCs include a decimation filter that is a
third-order sinc (or notch) filter. This filter processes the
multi-bit stream into either 16-bit or 24-bit words,
depending on the configuration chosen. The settling
time of the filter is three DMCLK periods. The resolution
achievable at the output of the sinc filter (the output of
the ADC) is dependent on the oversampling ratio
selected.
22.1.4.1
The AFE contains an internal voltage reference source
specially designed to minimize drift over temperature.
This internal V
channels. The typical value of this voltage reference is
2.37V ±2%. The internal reference has a very low typi-
cal temperature coefficient of ±12 ppm/°C, allowing the
output codes to have minimal variation with respect to
temperature since they are proportional to (1/V
The output pin for the internal voltage reference is
REFIN+/OUT.
Optionally, the AFE can be configured to use an exter-
nal voltage reference supplied on the REFIN+ and
REFIN- pins.
22.1.5
The AFE incorporates a phase delay generator which
ensures that the two ADCs are converting the inputs
with a fixed delay between them. The two ADCs are
synchronously
modulator outputs is delayed, so that the SINC filter
outputs (thus, the ADC outputs) show a fixed phase
delay, configured by the PHASE register.
22.1.6
The AFE uses an external clock signal to operate its
internal digital logic. The AFE includes a clock genera-
tion chain of back-to-back dividers to produce a range
of sampling frequencies.
22.1.7
The AFE uses an SPI-compatible slave serial interface.
Its operation is discussed in Section 22.3 “Serial
Interface”.
SINC
PHASE DELAY BLOCK
INTERNAL AFE CLOCK
SERIAL INTERFACE
Internal Voltage Reference
REF
sampling
3
supplies reference voltage to both
FILTER
 2010 Microchip Technology Inc.
but
the
averaging
REF
of
).