PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 322

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
REGISTER 26-3:
DS39979A-page 322
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/WO-1
IESO
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
Unimplemented: Read as ‘0’
LPT1OSC: T1OSC/SOSC Power Selection Configuration bit
1 = High-power T1OSC/SOSC circuit is selected
0 = Low-power T1OSC/SOSC circuit is selected
T1DIG: T1CKI for Digital Input Clock Enable bit
1 = T1CKI is available as a digital input without enabling T1OSCEN
0 = T1CKI is not available as a digital input without enabling T1OSCEN
FOSC<2:0>: Oscillator Selection bits
111 = ECPLL OSC1/OSC2 as primary; ECPLL oscillator with PLL is enabled; CLKO on RA6
110 = EC OSC1/OSC2 as primary; external clock with F
101 = HSPLL OSC1/OSC2 as primary; high-speed crystal/resonator with software PLL control
100 = HS OSC1/OSC2 as primary; high-speed crystal/resonator
011 = INTPLL1 internal oscillator block with software PLL control; F
010 = INTIO1 internal oscillator block with F
001 = INTPLL2 internal oscillator block with software PLL control and I/O on RA6 and RA7
000 = INTIO2 internal oscillator block with I/O on RA6 and RA7
R/WO-1
FCMEN
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
WO = Write-Once bit
U-0
—
LPT1OSC
R/WO-1
Preliminary
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
OSC
R/WO-1
T1DIG
/4 output on RA6 and I/O on RA7
OSC
/4 output
R/WO-1
FOSC2
OSC
 2010 Microchip Technology Inc.
/4 output
‘0’ = Bit is cleared
R/WO-1
FOSC1
R/WO-1
FOSC0
bit 0