PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 243

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

19.2
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)
selects 16-bit mode.
The SPBRGH1:SPBRG1 register pair controls the
period of a free-running timer. In Asynchronous mode,
BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>) bits
also control the baud rate. In Synchronous mode, BRGH
is ignored. Table 19-1 shows the formula for computa-
tion of the baud rate for different EUSART modes that
only apply in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGH1:SPBRG1 registers can
be calculated using the formulas in Table 19-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 19-1. Typical baud rates
and error values for the various Asynchronous modes
are shown in Table 19-2. It may be advantageous to use
TABLE 19-1:
EXAMPLE 19-1:
TABLE 19-2:
 2010 Microchip Technology Inc.
Legend: x = Don’t care, n = Value of SPBRGH1:SPBRG1 register pair
TXSTA1
RCSTA1
BAUDCON1
SPBRGH1
SPBRG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate = F
Solving for SPBRGH1:SPBRG1:
Calculated Baud Rate=16000000/(64 (25 + 1))
Error
SYNC
Name
0
0
0
0
1
1
X
EUSART Baud Rate Generator
(BRG)
=
=
=
=
=
=
Configuration Bits
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
ABDOVF
((F
((16000000/9600)/64) – 1
[25.042] = 25
9615
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
BRG16
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
OSC
OSC
0
0
1
1
0
1
/Desired Baud Rate)/64) – 1
CALCULATING BAUD RATE ERROR
OSC
of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
/(64 ([SPBRGH1:SPBRG1] + 1))
RCMT
Bit 6
RX9
TX9
BRGH
0
1
0
1
x
x
OSC
RXDTP
SREN
TXEN
Bit 5
, the nearest
TXCKP
SYNC
CREN
Bit 4
Preliminary
BRG/EUSART Mode
16-bit/Asynchronous
16-bit/Asynchronous
16-bit/Synchronous
8-bit/Asynchronous
8-bit/Asynchronous
8-bit/Synchronous
SENDB
ADDEN
BRG16
Bit 3
PIC18F87J72 FAMILY
the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
Writing a new value to the SPBRGH1:SPBRG1 regis-
ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before
SPBRGH1:SPBRG1 values of 0000h and 0001h are
not supported in Synchronous mode.
19.2.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG1 register pair.
19.2.2
The data on the RX1 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX1 pin.
BRGH
FERR
Bit 2
—
outputting
OPERATION IN POWER-MANAGED
MODES
SAMPLING
OERR
TRMT
WUE
Bit 1
the
Baud Rate Formula
F
F
ABDEN
F
RX9D
OSC
OSC
TX9D
Bit 0
OSC
new
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
DS39979A-page 243
Reset Values
baud
on Page
51
51
53
53
51
rate.