PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 286

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
22.3
22.3.1
All communication with the dual-channel AFE is
handled through its serial interface; this includes the
exchange of data with the PIC18F8XJ72 device itself.
This arrangement allows the AFE to direct data with
other microcontrollers on an SPI bus in complex appli-
cations, and work cooperatively with other SPI enabled
analog devices.
The serial interface is an SPI-compatible slave inter-
face, compatible with SPI modes, 0,0 and 1,1. Data is
clocked out of the AFE on the falling edge of SCKA
and, clocked into the device on the rising edge of
SCKA. In these modes, SCKA can Idle either high or
low.
A complete discussion of the serial interface is pro-
vided in Section B.5 “Serial Interface Description” of
the AFE Reference.
22.3.2
The first byte transmitted to the AFE is always a control
byte. This byte is composed of three fields
(Figure 22-2):
• Two address bits (A<6:5>, the MSbs)
• Five register address bits (A<4:0>)
• One Read/Write bit (R/W, the LSbs)
The AFE interface is device-addressable (through
A<6:5>), so that multiple devices can be present on the
same SPI bus with no data bus contention. This
functionality allows external SPI Master devices on the
bus, such as another microcontroller, to read and share
data. It also enables three-phase power metering
systems containing two additional analog front end
devices, controlled by a single SPI bus (single CS,
SCK, SDI and SDO pins).
The SPI device address bits of the PIC18F87J72
interface are always ‘00’; they cannot be changed.
FIGURE 22-2:
A read on undefined addresses gives an output of all
zeros on the first and all subsequent transmitted bytes.
Writing to an undefined address has no effect and does
not increment the address counter either.
DS39979A-page 286
A6
Address
Device
Bits
Serial Interface
A5
OVERVIEW
CONTROL BYTE
A4
A3
Address Bits
CONTROL BYTE
Register
A2
A1
A0
Write Bit
R/W
Read
Preliminary
22.3.3
The first data byte read is the one defined by the
address given in the control byte. After this first byte is
transmitted, if the CSA pin is held low, the communica-
tion continues and the address of the next transmitted
byte is determined by the configuration of the interface,
set by the read bits in the STATUS/COM register.
22.3.4
The first data byte written is the one defined by the
address given in the control byte. The write
communication automatically increments the address
for subsequent bytes.
The address of the next transmitted byte within the
same communication (CSA stays low) is the next
address defined on the register map. At the end of the
register map, the address loops to the beginning of the
register map. Writing a non-writable register has no
effect.
The SDOA pin remains in a high-impedance state
during a write communication.
22.3.5
If the user wishes to read back one or both of the ADC
channels continuously, the internal address counter of
the AFE can be set to loop on specific register sets.
This method also makes it possible to continuously
read specific register groups, one of the register types
or all of the registers.
In each case, one control byte on SDIA starts the
communication. The part stays within the same loop
until CSA returns high.
Continuous communication is described in more detail
in Section B.5.7 “Continuous Communication,
Looping On Address Sets” of the AFE Reference.
22.3.6
In addition to the standard SPI interface pins (SDIA,
SDOA, SCKA and CSA), the AFE provides an addi-
tional Data Ready (DR) signal. This signifies to an
external device when conversion data is available. The
DR signal, available on the pin of the same name, is an
active-low pulse at the end of a channel conversion,
with a period that is equal to the DRCLK clock period
and with a width equal to one DMCLK period.
The DR pin can be configured to operate in different
modes that are defined by the availability of conversion
data on the ADC channels. The various Data Ready
modes and configuration options for the DR pin are
described in Section B.5.9 “Data Ready Pin (DR)” of
the AFE Reference.
READING FROM THE DEVICE
WRITING TO THE DEVICE
CONTINUOUS COMMUNICATION
AND LOOPING ON ADDRESS SETS
DATA READY PIN (DR)
 2010 Microchip Technology Inc.