PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 262

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

integer value for the SPBRG2 register can be calculated
PIC18F87J72 FAMILY
20.2
The BRG is a dedicated, 8-bit generator that supports
both the Asynchronous and Synchronous modes of the
AUSART.
The SPBRG2 register controls the period of a
free-running timer. In Asynchronous mode, the BRGH
(TXSTA<2>) bit also controls the baud rate. In
Synchronous mode, BRGH is ignored. Table 20-1
shows the formula for computation of the baud rate for
different AUSART modes, which only apply in Master
mode (internally generated clock).
Given the desired baud rate and F
using the formulas in Table 20-1. From this, the error in
baud rate can be determined. An example calculation is
shown in Example 20-1. Typical baud rates and error
values for the various Asynchronous modes are shown
in Table 20-2. It may be advantageous to use the high
baud rate (BRGH = 1) to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
TABLE 20-1:
EXAMPLE 20-1:
TABLE 20-2:
DS39979A-page 262
Legend: x = Don’t care, n = Value of SPBRG2 register
TXSTA2
RCSTA2
SPBRG2
Legend: Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate = F
Solving for SPBRG2:
Calculated Baud Rate=16000000/(64 (25 + 1))
Error
Name
SYNC
Configuration Bits
X
0
0
1
AUSART Baud Rate Generator
(BRG)
AUSART Baud Rate Generator Register
=
=
=
=
=
=
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
((F
((16000000/9600)/64) – 1
[25.042] = 25
9615
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
OSC
BRGH
OSC
CALCULATING BAUD RATE ERROR
OSC
of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
0
1
x
/Desired Baud Rate)/64) – 1
/(64 ([SPBRG2] + 1))
Bit 6
TX9
RX9
OSC
SREN
TXEN
Bit 5
, the nearest
BRG/AUSART Mode
Asynchronous
Asynchronous
Synchronous
Preliminary
CREN
SYNC
Bit 4
ADDEN
Writing a new value to the SPBRG2 register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
20.2.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG2 register.
20.2.2
The data on the RX2 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present on the RX2 pin.
Bit 3
—
BRGH
FERR
Bit 2
OPERATION IN POWER-MANAGED
MODES
SAMPLING
OERR
TRMT
Baud Rate Formula
Bit 1
 2010 Microchip Technology Inc.
F
F
F
OSC
OSC
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
RX9D
TX9D
Bit 0
Values on
Reset
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