PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet - Page 439

• Manufacturer Part Number: PIC18F87J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE B-2:
Note:
B.3.5
The ratio of the sampling frequency to the output data
rate, OSR = DMCLK/DRCLK. The default OSR is 64, or
with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4 MHz,
f
CONFIG1 register are used to change the oversampling
ratio (OSR).
TABLE B-3:
B.3.6
This is the error induced by the ADC when the inputs
are shorted together (VIN = 0V). The specification
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip
to chip. This offset error can easily be calibrated out by
a MCU with a subtraction. The offset is specified in mV.
The offset on the dual-channel AFE has a low
temperature coefficient.
 2010 Microchip Technology Inc.
S
PRE<1:0>
= 1 MHz, f
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
OSR<1:0>
0
0
1
1
CONFIG
For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1.
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
OSR – OVERSAMPLING RATIO
OFFSET ERROR
0
1
0
1
D
= 15.625 ksps. The following bits in the
OSR<1:0>
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE
OVERSAMPLING RATIO
SETTINGS
OVERSAMPLING RATIO
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OSR
256
128
256
128
256
128
256
128
64 (default)
64
32
64
32
64
32
64
32
(OSR)
128
256
32
AMCLK
MCLK/8
MCLK/8
MCLK/8
MCLK/8
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK
MCLK
MCLK
MCLK
Preliminary
MCLK/32
MCLK/32
MCLK/32
MCLK/32
MCLK/16
MCLK/16
MCLK/16
MCLK/16
DMCLK
MCLK/8
MCLK/8
MCLK/8
MCLK/8
MCLK/4
MCLK/4
MCLK/4
MCLK/4
PIC18F87J72 FAMILY
B.3.7
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in per-
cent compared to the ideal transfer function defined by
Equation B-15. The specification incorporates both
PGA and ADC gain error contributions, but not the
V
V
The gain error of the dual-channel AFE has a low
temperature coefficient.
B.3.8
Integral nonlinearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed, or with the endpoints equal to zero.
It is the maximum remaining error after calibration of
offset and gain errors for a DC input signal.
B.3.9
For the AFE, the signal-to-noise ratio is a ratio of the
output fundamental signal power to the noise power
(not including the harmonics of the signal), when the
input is a sine wave at a predetermined frequency. It is
measured in dB. Usually, only the maximum signal to
noise ratio is specified. The SNR figure depends mainly
on the OSR and DITHER settings of the device.
REF
REF
MCLK/8192
MCLK/4096
MCLK/2048
MCLK/1024
MCLK/4096
MCLK/2048
MCLK/1024
MCLK/2048
MCLK/1024
MCLK/1024
MCLK/512
MCLK/512
MCLK/256
MCLK/512
MCLK/256
MCLK/128
).This error varies with PGA and OSR settings.
DRCLK
contribution (it is measured with an external
GAIN ERROR
INTEGRAL NON-LINEARITY ERROR
SIGNAL-TO-NOISE RATIO (SNR)
DRCLK
0.4882
7.8125
7.8125
15.625
7.8125
15.625
(ksps)
0.976
0.976
31.25
1.95
1.95
1.95
3.9
3.9
3.9
3.9
SINAD
(dB)
68.2
68.2
91.4
86.6
91.4
86.6
78.7
91.4
86.6
78.7
91.4
86.6
78.7
78.7
68.2
68.2
DS39979A-page 439
ENOB
14.89
14.10
12.78
14.89
14.10
12.78
14.89
14.10
12.78
14.89
14.10
12.78
(bits)
11.04
11.04
11.04
11.04