WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 138

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1.5
7.1.5.1
Note:
7.1.5.2
Note:
138
Packet Split Receive Descriptor
The 82574L uses the packet split feature when the RFCTL.EXSTEN bit is set and
RCTL.DTYP=01b. The software device driver must also program the buffer sizes in the
PSRCTL register.
Descriptor Read Format:
Buffer Addresses [3:0] (4 x 64 bit)
The physical address of each buffer is written in the Buffer Addresses fields. The sizes
of these buffers are statically defined by BSIZE0-BSIZE3 in the PSRCTL register.
DD (1-Bit, Offset 8.0)
The software device driver might use the DD bit from the Status field to determine
when a descriptor has been used. Therefore, the software device driver must ensure
that the Least Significant B (LSB) of Buffer Address 1 is zero. This should not be an
issue, since the buffers should be page aligned for the packet split feature to be useful.
Any software device driver that cannot align buffers should not be using this descriptor
format.
Software Notes:
16
24
0
8
• All buffers' addresses in a packet split descriptor must be word aligned.
• Packet header can't span across buffers, therefore, the size of the first buffer must
• If software sets a buffer size to zero, all buffers following that one should be set to
• When configured to packet split and a given packet spans across two or more
be larger than any expected header size. Otherwise the packet will not be split.
zero as well. Pointers in the packet split receive descriptors to buffers with a zero
size should be set to any address, but not to NULL pointers. Hardware does not
write to this address.
packet split descriptors, the first buffer of any descriptor (other than the first one)
is not used.
63
Buffer Address 1
Buffer Address 0
Buffer Address 2
Buffer Address 3
82574 GbE Controller—Inline Functions
0
0