WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 349

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.6.10
It is reloaded to its high (last written) value when it decreased below zero.
When the counter reaches zero, other TX queues should be selected for transmission as
soon as possible (usually after current transmission).
COMP is the enable bit to compensate between the two queues, when enabled (set to
1b) hardware compensates between the two queues if one of the queues is
transmitting TCP segmentation packets and its counter went below zero, hardware
compensates the other queue according to the ratio in the opposite TARC.RATIO
register.
For example, if the TARC0.COUNT reached (-5) after sending TCP segmentation
packets and both TARC0.COMP and TARC1.COMP are enabled (set to 1b) and
TARC1.RATIO is 01b (1/2 compensation) TARC1.COUNT is adjusted by adding 5/2=2 to
the current count.
RATIO is the multiplier to compensate between the two queues. The compensation
method is described in the previous explanation.
Transmit Interrupt Delay Value - TIDV (0x03820; RW)
This register is used to delay interrupt notification for transmit operations by coalescing
interrupts for multiple transmitted buffers. Delaying interrupt notification helps
maximize the amount of transmit buffers reclaimed by a single interrupt. This feature
ONLY applies to transmit descriptor operations where:
This feature operates by initiating a count-down timer upon successfully transmitting
the buffer. If a subsequent transmit delayed-interrupt is scheduled BEFORE the timer
expires, the timer is re-initialized to the programmed value and re-starts its count
down. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated.
Setting the value to 0b is not allowed. If an immediate (non-scheduled) interrupt is
desired for any transmit descriptor, the descriptor IDE should be set to 0b.
The occurrence of either an immediate (non-scheduled) or absolute transmit timer
interrupt halts the TIDV timer and eliminate any spurious second interrupts.
IDV
Reserved
FPD
1. Interrupt-based reporting is requested (RS set).
2. The use of the timer function is requested (IDE is set).
• Upon a read, hardware returns the current counter value.
• Upon a write, the counter updates the high value in the next counter reload.
• The counter can be decreased in chunks (when transmitting TCP segmentation
packets). It should never roll because of that. The size of chunks is determined
according to the TCP segmentation (number of packets sent).
Field
15:0
30:16
31
Bit(s)
0x0
0x0
0b
Initial
Value
Interrupt Delay Value
Counts in units of 1.024 microseconds. A value of 0 is not allowed.
Reads as 0x0. Should be written to 0x0 for future compatibility.
Flush Partial Descriptor Block
When set to 1b, ignored. Reads as 0b.
Description
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