WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 165

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
Note:
7.2.10.1.5
7.2.10.1.6
Extended Command - ExtCMD
When IC is set, hardware inserts a checksum value calculated from the CSS bit value to
the CSE bit value, or to the end of packet. The checksum value is inserted in the header
at the CSO bit value location. One or many descriptors can be used to form a packet.
Checksum calculations are for the entire packet starting at the byte indicated by the
CSS field. A value of zero for CSS corresponds to the first byte in the packet. CSS must
be set in the first descriptor for a packet. In addition, IC is ignored if CSO or CSS are
out of range. This occurs if (
When IFCS is set, hardware appends the MAC FCS at the end of the packet. When
cleared, software should calculate the FCS for proper CRC check. The software must set
IFCS in the following instances:
EOP stands for end-of-packet and when set, indicates the last descriptor making up the
packet.
VLE, IFCS, CSO, and IC are qualified by EOP. In other words, hardware interprets these
bits ONLY when the EOP bit is set.
RSV (bit 3:1) - Reserved
TS (bit 0) - Time stamp
The TS bit indicates to the 82574 to put a time stamp on the packet designated by the
descriptor.
Status - STA
RSV (bit 3:1) - Reserved
DD (bit 0) - Descriptor done status
DD indicates that the descriptor is done and is written back after the descriptor has
been processed (assuming the RS bit was set). The DD bit can be used as an indicator
to the software that all descriptors, in the memory descriptor ring, up to and including
the descriptor with the DD bit set are again available to the software.
• Transmission of short packets while padding is enabled by the TCTL.PSP bit
• Checksum offload is enabled by the IC bit in the TDESC.CMD
• VLAN header insertion enabled by the VLE bit in the TDESC.CMD
• Large send or TCP/IP checksum offload using context descriptor
3
3
Rsv
Rsv
2
2
CSS Length
1
1

DD
) or (
TS
0
0
CSO Length 1

–
).
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