WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 327

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
Note:
10.2.5
10.2.5.1
If invalid values are written to the INT_Alloc fields the result is unexpected.
Receive Register Descriptions
Receive Control Register - RCTL (0x00100; RW)
INT_Alloc[4]
INT_Alloc_val[4] 19
Reserved
Interrupt_on_all
_WB
Reserved
EN
SBP
UPE
MPE
LPE
LBM
Field
Field
0
1
2
3
4
5
7:6
Bit(s)
18:16
30:20
31
Bit(s)
0x0
0
0x0
0b
0b
0b
0b
0b
0b
0b
00b
Initial
Value
Initial
Value
Defines the MSI-X vector assigned to the interrupt cause associated
with this entry. Valid values are 0 to 4 for MSI-X mode.
Note: Mapped to Other Cause. Other Cause associates an interrupt
issued by other causes with a corresponding entry in the MSI-X
Allocation registers.
Enable bit for Other Cause.
Reserved
If set, Tx interrupts occur on every write back, regardless of the RS
bit.
Reserved
This bit represented as a hardware reset of the receive-related
portion of the device in previous controllers, but is no longer
applicable. Only a full device reset CTRL.RST is supported. Write as 0b
for future compatibility.
Enable
The receiver is enabled when this bit is set to 1b. Writing this bit to
0b, stops reception after receipt of any in progress packet. All
subsequent packets are then immediately dropped until this bit is set
to 1b.
Store Bad Packets
0b = Do not store
1b = Store.
Note that CRC errors before the SFD are ignored. Any packet must
have a valid SFD (RX_DV with no RX_ER in the GMII/MII i/f) in order
to be recognized by the device (even bad packets).
Note: Bad packets are not routed to manageability even if this bit is
set.
Unicast Promiscuous Enable
0b = Disabled.
1b = Enabled.
Multicast Promiscuous Enable
0b = Disabled.
1b = Enabled.
Long Packet Enable.
0b = Disabled.
1b = Enabled.
Loopback mode
Should always be set to 00b.
00b = Normal operation (or PHY loopback in GMII/MII mode).
01b = MAC Loopback (test mode).
10b = Undefined.
11b = Undefined.
Description
Description
327