WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 190

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.7.2
190
The 1588 standard specifically addresses the needs of measurement and control
systems:
The time sync mechanism activation is possible in full-duplex mode and with extended
descriptors only. No limitations on the wire speed although the wire speed might affect
the accuracy.
Flow and Hardware/Software Responsibilities
The operation of a Precision Time Protocol (PTP) enabled network is divided into two
stages, Initialization and time synchronization.
At the initialization stage every master enabled node starts by sending sync packets
that include the clock parameters of its clock. Upon receipt of a sync packet a node
compares the received clock parameters to its own and if the received parameters are
better, then this node moves to slave state and stops sending sync packets. When in
slave state the node continuously compares the incoming packet to its currently chosen
master and if the new clock parameters are better then the master selection is
transferred to this master clock. Eventually the best master clock is chosen. Every node
has a defined time-out interval in which if no sync packet was received from its chosen
master clock it moves back to master state and starts sending sync packets until a new
Best Master Clock (BMC) is chosen.
The time synchronization stage is different to master and slave nodes. If a node is at
master state it should periodically send a sync packet which is time stamped by
hardware on the Tx path (as close as possible to the PHY). After the sync packet a
Follow_Up packet is sent that includes the value of the timestamp kept from the sync
packet. In addition the master should timestamp Delay_Req packets on its Rx path and
return to the slave that sent it the timestamp value using a Delay_Response packet. A
node in slave state should timestamp every incoming sync packet and if it came from
its selected master, software uses this value for time offset calculation. In addition it
should periodically send Delay_Req packets in order to calculated the path delay from
its master. Every sent Delay_Req packet sent by the slave is time stamped and kept.
With the value received from the master with Delay_Response packet the slave can
now calculate the path delay from the master to the slave. The synchronization
protocol flow and the offset calculation are shown in
• Spatially localized
• s to sub-s accuracy
• Administration free
• Accessible for both high-end devices and low-cost, low-end devices
Figure
82574 GbE Controller—Inline Functions
42.