WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 53

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interconnects—82574 GbE Controller
3.2.6.4
Note:
Note:
3.3
3.3.1
3.3.2
Software Initiated Pause Frame Transmission
The 82574L has the added capability to transmit an XOFF frame via software. This is
accomplished by software writing a 1b to the SWXOFF bit of the Transmit Control
register. Once this bit is set, hardware initiates transmitting a pause frame in a manner
similar to that automatically generated by hardware.
The SWXOFF bit is self-clearing after the pause frame has been transmitted.
The state of the CTRL.TFCE bit or the negotiated flow control configuration does not
affect software generated pause frame transmission.
Software sends an XON frame by programming a zero in the Pause Timer field of the
FCTTV register.
XOFF transmission is not supported in 802.3x for half-duplex links. Software should not
initiate an XOFF or XON transmission if the 82574 is configured for half-duplex
operation.
SPI Non-Volatile Memory Interface
General Overview
The 82574L requires non-volatile content for the 82574 configuration. The Non-Volatile
Memory (NVM) might contain the following main regions:
Supported NVM Devices
Some Intel LAN controllers require both an EEPROM and Flash device for storing LAN
data. However, the 82574 reduces the Bill of Material (BOM) cost by consolidating the
EEPROM and Flash into a single non-volatile memory device. The NVM is connected to a
single Serial Peripheral Interface (SPI).
The 82574 is compatible with many sizes of 4-wire SPI NVM devices. The required NVM
size is dependent upon system requirements.
• LAN configuration space accessed by hardware - loaded by the 82574 after power
• LAN configuration space accessed by software - used by software only. The
up, PCI reset de-assertion, D3->D0 transition, or a software commanded EEPROM
read (CTRL_EXT.EE_RST).
meaning of these registers as listed here as a convention for the software only and
is ignored by the 82574.
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