WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 156

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.2
7.2.3
156
Transmission Flow Using Simplified Legacy Descriptors
Transmission Process Flow Using Extended Descriptors
The 82574L supports extended Tx descriptors that provide more offload capabilities.
The extended offload capabilities are indicated to the hardware by two types of
descriptors: context descriptors and data descriptors. The context descriptors define a
set of offload capabilities applicable for multiple packets while the data descriptors
define the data buffers and specific off load capabilities per packet.
The software/hardware flow while using the extended descriptors is as follows:
The software/hardware flow for TCP segmentation using the extended descriptors is as
follows:
1
2
3
4
5
6
7
10
11
12
13
• Software prepares the context descriptor that defines the offload capabilities for
• Software prepares the data packets in host memory within one or more data
• All steps are the same as the legacy Tx descriptors as previously described
• Software prepares the context descriptor that defines the upcoming TCP
• Software places a prototype header in host memory and indicates it to the
the incoming packets.
buffers and their descriptors.
(starting at step number 4) while the data buffers belong to a single packet.
segmentation, In this case, the data buffers belong to multiple packets.
hardware by a data descriptor.
Software defines a descriptor ring and configures the 82574's transmit queue with the address
location, length, head, and tail pointers of the ring. This step is executed once per Tx descriptor ring.
See
Software prepares the packet headers and data for the transmit within one or more data buffers.
Software prepares Tx descriptors according to the number of data buffers that are used. Each
descriptor points to a different data buffer and holds the required hardware processing. See
section 7.2.10
correct location in the Tx descriptor ring.
Software updates the transmit descriptor tail pointer (TDT) to indicate the hardware that Tx
descriptors are ready.
Hardware senses a change of the TDT and initiates a PCIe request to fetch the descriptors from host
memory.
The descriptors’ content is received in a PCIe read completion and is written to the appropriate
location in the descriptor queue.
According to the descriptors content the corresponding memory data buffers are then fetched from
the host to the hardware on-chip transmit FIFO.
While the packet is passing through the DMA and MAC units, relevant off load functions are
incorporated according to the commands in the descriptors.
After the entire packet is fetched by the hardware it is transmitted to the Ethernet link.
After a DMA of each buffer is complete, if the RS bit in the command byte is set, the DMA updates the
Status field of the appropriate descriptor and writes back the descriptor to the descriptor ring in host
memory.
The hardware moves the transmit descriptor head pointer (TDH) in the direction of the tail to point to
the next descriptor in the ring.
After the entire packet is fetched by the hardware an interrupt might be generated by the hardware to
notify the software device driver that it can release the relevant buffers to the operating system.
section 7.2.4
for more details on the descriptor format. The software places the descriptors in the
for more details on the descriptor ring structure.
82574 GbE Controller—Inline Functions