WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 90

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4.4.3
Note:
5.4.4.3.1
90
Dr State
Transition to Dr state is initiated on three occasions:
The 82574L meets the restrictions on using auxiliary power, defined in the PCI-PM
specification:
The restrictions apply to all cases of Dr state (power up, D3 entry, Dr entry from D0).
When the wake configuration is unknown (for example, during power up before an NVM
read), the 82574 must meet the 20 mA limit.
The system might maintain PE_RST_N asserted for an arbitrary time. The de-assertion
(rising edge) of PE_RST_N causes a transition to D0u state.
Any Wake-up filter settings that were enabled before entering this reset state are
maintained.
Entry to Dr State
Dr entry on platform power up begins by asserting the internal power detection circuit
(Internal Power On Reset). The NVM is read and determines device configuration. If the
APM Enable bit in the NVM's Initialization Control Word 2 is set, then APM wake up is
enabled. The PHY and MAC states are determined by the state of manageability and
APM wake. To reduce power consumption, if manageability or APM wake is enabled, the
PHY auto-negotiates to a lower link speed on Dr entry (see
PCIe link is not enabled in Dr state following system power up (since PERS# is
asserted).
Entry to Dr state from D0a state is by asserting the PE_RST_N signal. An ACPI
transition to the G2/S5 state is reflected in a device transition from D0a to Dr state.
The transition might be orderly (for example, the designer selected the shut down
option), in which case the software device driver might have a chance to intervene. Or,
it might be an emergency transition (such as, power button override), in which case,
the software device driver is not notified.
To reduce power consumption, if any of manageability, APM wake or PCI-PM PME is
enabled, the PHY auto-negotiates to a lower link speed on D0a to Dr transition (see
Section
Transition from D3 state to Dr state is done by asserting the PE_RST_N signal. Prior to
that, the system initiates a transition of the PCIe link from the L1 state to either the L2
or L3 state. The link enters L2 state if PCI-PM PME is enabled.
1. If wake is enabled (either APM wake, ACPI wake, or manageability), then the
2. If wake is disabled, then the 82574 might consume up to 20 mA @ 3.3 V dc.
• At system power up - Dr state begins with the assertion of the internal power
• At transition from a D0a state - During operation, the system might assert PCIe
• At transition from a D3 state - The system transitions the device into the Dr state
detection circuit (Internal Power On Reset) and ends with the assertion of the
Internal Pwrgd signal (indicating that the system de-asserted its PCIe PE_RST_N
signal).
PE_RST_N at any time. In an ACPI system, a system transition to the G2/S5 state
causes a transition from D0a to Dr state.
by asserting PCIe PE_RST_N.
82574 might consume up to 375 mA @ 3.3 V dc.
5.4.4.3.1).
82574 GbE Controller—Power Management and Delivery
Section
5.4.4.3.1). The