WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 348

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
Note:
10.2.6.8
Note:
10.2.6.9
348
If software were to write to this register while the transmit function was enabled, the
on-chip descriptor buffers might be invalidated and the hardware could be become
unstable.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00430.
Transmit Descriptor Tail - TDT (0x03818 + n*0x100[n=0..1]; RW)
This register contains the tail pointer for the transmit descriptor ring. It points to a 16-
byte datum. Software writes the tail pointer to add more descriptors to the transmit
ready queue. Hardware attempts to transmit all packets referenced by descriptors
between head and tail.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00438.
Transmit Arbitration Count - TARC (0x03840 + n*0x100[n=0..1]; RW)
COUNT is the transmit arbitration counter value.
The counter is subtracted as a part of the transmit arbitration.
TDT
Reserved
COUNT
COMP
RATIO
ENABLE
Reserved
Reserved
Reserved
Field
Field
15:0
31:16
6:0
7
9:8
10
26:11
30:27
31
Bit(s)
Bit(s)
0x0
0x0
0x3
0b
00b
1b
0x0
0000b
0b
Initial
Initial
Value
Value
Transmit Descriptor Tail
Reads as 0. Should be written to 0 for future compatibility.
Transmit Arbitration Count
The number of packets that can be sent from queue to make the N
over M arbitration between the queues.
Writing 0x0 to this register is not allowed.
Compensation Mode
When set to 1b, hardware compensates this queue according to the
compensation ratio if the number of packets in a TCP segmentation in
opposite queue caused the counter in that queue to go below zero.
Compensation Ratio
This value determines the ratio between the number of packets
transmitted on the opposite queue in a TCP segmentation offload to
the number of the packets that are added to this queue as
compensation.
00b = 1/1 compensation.
01b = 1/2 compensation.
10b = 1/4 compensation.
11 = 1/8 compensation.
Descriptor Enable
The Enable bit of transmit queue 0 should always be set.
Reserved, Reads as 0. Should be written to 0 for future compatibility.
Reserved
Reads as 0b. Should be written to 0b for future compatibility.
82574 GbE Controller—Driver Programing Interface
Description
Description