WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 21

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Interface—82574 GbE Controller
2.2
2.3
2.3.1
Table 7.
Pull-Up/Pull-Down Resistors and Strapping Options
Signal Type Definition
PCIe
PCIe
PECLKp
PECLKn
PE_Tp
PE_Tn
In
Out (O)
T/s
S/t/s
O/d
A-in
A-out
B
NC-SI_in
NC-SI_out
• As stated in the Name and Function table columns, the internal Pull-Up/Pull-Down
• Only relevant (digital) pins are listed; analog or bias and power pins have specific
• NVMT and AUX_PWR are used for a static configuration. They are sampled while
Symbol
(PU/PD) resistor values are 30 K ± 50%.
considerations listed in
PE_RST_N is active and latched when PE_RST_N is deasserted. At other times,
they revert to their standard usage.
Input is a standard input-only signal.
Totem pole output is a standard active driver.
Tri-State is a bi-directional, tri-state input/output pin.
Sustained tri-state is an active low tri-state signal owned and driven by one and only one agent
at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock before
letting it float. A new agent cannot start driving an s/t/s signal any sooner than one clock after
the previous owner tri-states it.
Open drain enables multiple devices to share as a wire-OR.
Analog input signals.
Analog output signals.
Input bias.
NC-SI input signal.
NC-SI output signal
26
25
21
20
Lead #
A-in
A-out
Type
Section
Input
Output
Mode
Op
12.0.
PCIe Differential Reference Clock In
This pin receives a 100 MHz differential clock input. This clock
is used as the reference clock for the PCIe Tx/Rx circuitry and
by the PCIe core PLL to generate a 125 MHz clock and 250
MHz clock for the PCIe core logic.
PCIe Serial Data Output
Serial differential output link in the PCIe interface running at
2.5 Gb/s. This output carries both data and an embedded 2.5
GHz clock that is recovered along with data at the receiving
end.
Name and Function
21