WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 75

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Initialization—82574 GbE Controller
Figure 19.
Table 31.
Global Reset Timing Diagram
Notes to Global Reset Timing Diagram
1
2
3
4
5
6
7
8
9
10
PCIe reference
Note
PCIe Link up
NVM Load
PHY State
D-State
PERST#
Wake
clock
The system must assert PE_RST_N before stopping the PCIe reference clock. It
must also wait tl2clk after link transition to L2/L3 before stopping the reference
clock.
On assertion of PE_RST_N, the 82574 transitions to Dr state and the PCIe link
transition to electrical idle. The PHY state is defined by the wake and
manageability configuration.
The system starts the PCIe reference clock tPWRGD-CLK before de-assertion
PE_RST_N.
De-assertion of PE_RST_N causes the NVM to be re-read, asserts PHY power-
down, and disables wake up.
After reading the NVM base area, PHY reset is de-asserted. APM wake might be
enabled.
Link training starts after the NVM was fully read (including extended
configuration if needed).
Link training starts after tpgtrn from PE_RST_N de-assertion.
A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-
assertion.
A first PCI configuration response can be sent after tpgres from PE_RST_N de-
assertion.
Writing a 1b to the Memory Access Enable bit in the PCI Command register
transitions the device from D0u to D0 state.
Active
L0
D0a
1
2
tclkpg
Any mode
Active / Down
Dr
3
t
PWRGD-CLK
4
Read
Auto
5
tee
Ext.
Conf.
6
tpgtrn
7
tpgcfg
8
APM
D0u
tpgres
L0
9
10
D0a
75