WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 347

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
Note:
10.2.6.5
Note:
10.2.6.6
Note:
10.2.6.7
This register contains the lower bits of the 64-bit descriptor base address. The lower
four bits are ignored. The transmit descriptor base address must point to a 16-byte
aligned block of data.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00420.
Transmit Descriptor Base Address High - TDBAH (0x03804 +
n*0x100[n=0..1]; RW)
This register contains the upper 32 bits of the 64-bit descriptor base address.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00424.
Transmit Descriptor Length - TDLEN (0x03808+ n*0x100[n=0..1];
RW)
This register contains the descriptor length and must be 128-byte aligned.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00428.
Transmit Descriptor Head - TDH (0x03810 + n*0x100[n=0..1]; RW)
This register contains the head pointer for the transmit descriptor ring. It points to a
16-byte datum. Hardware controls this pointer. The only time that software should
write to this register is after a reset (hardware reset or CTRL.RST) and before enabling
the transmit function (TCTL.EN).
TDBAH
0
LEN
Reserved
TDH
Reserved
Field
Field
Field
31:0
6:0
19:7
31:20
15:0
31:16
Bit(s)
Bit(s)
Bit(s)
X
0x0
0x0
0x0
0x0
0x0
Initial
Initial
Initial
Value
Value
Value
Transmit Descriptor Base Address [63:32]
Ignore on write. Reads back as 0x0.
Descriptor Length
Reads as 0x0. Should be written to 0x0.
Transmit Descriptor Head
Reserved
Should be written with 0x0.
Description
Description
Description
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